1. Field of the Invention
The present invention relates to a self-testing semiconductor device such as a large-scale integrated circuit having a self-testing function and, more particularly, to a semiconductor device having a testing function to test itself or a semiconductor device having an testing circuit attached to the outer periphery of the device to inspect it.
2. Description of the Related Art
In recent years, large scale semiconductor devices, such as VLSIs, having greater scales and higher device densities have been manufactured. These new semiconductor devices have full functions and high availabilities. On the other hand, their circuit configurations are complex, and an exorbitant effort of inspection is needed to judge whether each manufactured semiconductor device is operating within normal parameters. Consequently, a considerable amount of time and much labor have been required to this end. For example, a multiplier with a binary 32-bit output is a combinatorial logic circuit having 16 bits.times.2 inputs and a 32-bit output. This multiplier is a functional LSI comprising AND gates, OR gates, inverters (NOT gates), buffers, switches, etc. The total number of gates reaches about 6500. With a functional check, the number of input data combinations amounts to as many as 2.sup.32. Therefore, even if each data item is checked at a speed of 50 MHz, it takes about 85.9 seconds to complete the testing. Also, it is uneconomical and unrealistic to previously hold such a large amount of data.
Accordingly, in an attempt to solve this kind of problem, so-called self-testing semiconductor devices of various constructions have been proposed as described in Japanese Patent Laid-Open No. 68624/1985. Such a self-testing semiconductor device consists of a chip having a built-in testing circuit. This test is known as a built-in self-test (BIST). These self-testing devices have been put into practical use by various manufacturers since the late 1980s.
The fundamental idea of the built-in testing device is to construct both a testing data generator and a output data compressor inside the chip. More specifically, combinations of input data items generated by the testing data generator are loaded as testing data patterns into each semiconductor device to be inspected. The resultant output of the testing are compressed and compared with the correct data obtained from a normal circuit. In this way, the device is judged whether it is good or not. However, the testing circuit added to the device occupies 5 to 10% of the chip area. Furthermore, the testing time is prolonged. Consequently, the cost of the chip is increased.
It is known that the use of a random data pattern for inspecting each semiconductor device is effective in inspecting circuits as described by T. W. Williams, E. B. Eichelberger in "Random Patterns within a Structured Sequential Logic Design." Dig. of Papers, Semi-conductor Test Symp., IEEE Pub. 77CH1261-7c, pp. 19-27, October, 1977. Therefore, in a proposed inspecting technique, a pseudo-random pattern is generated as a testing data pattern, thus performing testing. In this case, the inspected circuit produces a series of test results on each output line in response to the testing signal, or data about testing. If a fault exists in the circuit under test, the test results are different from expected values. Thus, the test results and the expected values are compared by a decision circuit, which determines whether the circuit is faulty or not. In the case of a large-scale combination logic circuit, the testing results are as large as hundreds of kilo-bits. The results are successively compared with expected values. This needs a large capacity of memory. Therefore, before each comparison, each result of inspection is compressed into several bits by a compression circuit. In the self-testing, a testing mechanism is built into a chip. Hence, it is important that the testing additional circuit be made compact. Even if the additional circuit is made compact, it is necessary to build a pseudo-random number-generating circuit for generating a testing data pattern and a circuit for compressing and comparing the results of testing into the chip, as shown in FIG. 1. Yet, the area occupied by the testing circuit is large. The amount of data about testing is large. In this way, the above-described problem is not yet sufficiently solved.
Japanese Patent Laid-Open No. 150874/1987 shows a circuit shown in FIG. 2. This self-testing circuit has a memory in which data used for inspecting each circuit is stored. Therefore, as the scale of the circuit under test becomes larger, data about inspection increases. As a result, the capacity of the memory must be increased.
In the aforementioned prior art self-testing LSI circuit, self-testing can be performed at a high speed, using a large amount of data about testing. However, a testing control circuit, a testing control memory, a test pattern memory, an arithmetic circuit for testing, a pattern comparator circuit, and a selector must be incorporated into the chip. Consequently, the ratio (hereinafter referred to as the overhead ratio) of the area of the whole testing circuit to the whole chip area is increased. As a result, the area of the LSI is increased.